1. Field of the Invention
The present invention is related to the field of integrated circuits. More particularly, the present invention is a method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays.
2. Art Background
Many integrated circuits (ICs) 10 today have both system logic 12 and embedded memory arrays 14 on a single chip (FIG. 1 ). The system logic 12 consists of all elements other than the embedded memory arrays 14. The system logic 12 may comprise combinational logic, flip-flops and latches. The embedded memory arrays 14 may comprise random access memory (RAM), read only memory (ROM) and first-in first-out serial memory (FIFO).
Traditionally, the focus for reducing the high cost associated with testing complex integrated circuits 10 has been on the system logic 12. The system logic 12 of an integrated circuit 10 typically incorporates a form of scan-based design for testability, such as full serial integrated scan or isolated serial scan. The various forms of scan-based design are used to increase the controllability and observability of the system logic 12, the two key measures of testability. As a result of enhanced controllability and/or observability, higher fault coverage of the system logic 12 is achieved.
Controllability is the ability to establish a specific signal at each node in a circuit by setting values on the circuit's input. Observability is the ability to determine the signal value at any node in a circuit by controlling the circuit's input and observing its outputs. Fault coverage is the ratio between the number of faults detectable and the total number of faults in the assumed fault universe. For further description on testability and scan-based designs, see M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990, pp. 343-346, 364-381.
Traditionally, no special effort is made to enhance the controllability and/or the observability of the embedded memory arrays 14 to improve the fault coverage of the system logic 12. The embedded memory arrays 14 are typically handled in one of three different ways:
1. The embedded memory arrays 14 simply output an unknown value (X), which is fed into the system logic 12 (FIG. 2a).
2. The embedded memory arrays 14 are surrounded with scan storage elements (SR) 16, such as flip-flops. The scan storage elements 16 are included in the scan chain (FIG. 2b).
3. The embedded memory arrays 14 are provided with a functional vector and outputs a test vector which is fed into the system logic 12 (FIG. 2c). The functional vector is loaded into the embedded memory arrays 14 in between scan vectors.
These traditional methods of handling the embedded memory all have draw backs. For the first method, the unknown values (Xs) feeding into the system logic tend to lower the fault coverage of the integrated circuit. For the second way, the extra scan storage elements impose additional hardware requirements and further delay the inputs and outputs of the embedded memory. For the third method, the loading of functional vectors may not be viable for an embedded memory with a relatively short fixed scan test cycle. Additionally, the loading of functional vectors may not be viable if the embedded memory arrays' controls bits are affected by the system logic.
As will be discussed, the present invention overcomes the disadvantages of the prior art and provides a method and apparatus for improving the fault coverage of system logic of an integrated circuit with embedded memory arrays by indirectly enhancing the controllability and observability of the system logic through enhancement to the controllability of the embedded memory arrays. The method and apparatus of the present invention achieves higher fault coverage of the system logic than the first aforementioned method, incurs less hardware/performance burden than the second method, and works with a relatively short fixed scan test cycle unlike the third method. Additionally, unlike the third method, the method and apparatus of the present invention also eliminates writing the functional vector by hand.